1. Field of the Invention
This invention relates generally to controlled collapse chip connection, and more particularly to providing a structure and method for implementing a tensile pull test of ball-limiting metallurgies (BLM), to determine the peel strength for Controlled-collapse chip connections (C4).
2. Description of the Background
Controlled-collapse chip connection (C4) is a means of connecting integrated circuit (IC) chips to substrates in electronic packages. C4 is known as a flip-chip technology, in which the interconnections are small solder balls on the bottom side chip surface. C4 technology represents one of the highest density schemes known in the art for chip interconnections. The C4 technology was initially developed in the 1960s and has proven reliable in the semiconductor field. Historically, the PbSn (lead-tin) solder for the formation of the solder ball was evaporated through a metal mask. In the 1990s, electrochemical fabrication of C4 interconnections was introduced. Electroplating is more extendible than evaporation to small C4-pad dimensions, closer pad spacing, larger wafers, and lower-melting solders (which have a higher content of tin (Sn)).
In general, the top layers of an integrated circuit (IC) chip are wiring levels, separated by insulating layers of dielectric material that provide input/output for the device. In C4 structures, the chip wiring is terminated by a plurality of metal films that form the ball-limiting metallurgy (BLM), which is also referred to as under-bump metallurgy (UBM). The ball-limiting metallurgy defines the size of the solder bump after reflow, provides a surface that is wettable by the solder, and that reacts with the solder to provide good adhesion and acceptable reliability under mechanical and heat stress. The BLM also serves as a barrier between the integrated-circuit device and the metals in the interconnection.
FIGS. 1A and 1B are a typical implementation of the C4 manufacturing process. In FIG. 1A an integrated circuit (IC) 100 formed on a base material 102 (for example, silicon) has a solder ball 108 formed for subsequent attachment to a contact pad 112 (see FIG. 1B) on a carrier 114. A BLM 106 constricts the solder flow and aids in the formation of the solder ball 108 (which is formed by reflowing a deposit of solder paste), and serves as a wettable surface and contact for an underlying contact 110 for the IC 100. A passivation layer 104, typically a polymer dielectric, insulates the IC 100, and supports the BLM 106. In FIG. 1B the IC 100 is attached to the contact pad 112 on the carrier 114, by reflowing the solder ball 108. Solder flow is restricted on the carrier 114 by solder dams 116, which outline and define the contact pad 112. A secondary reflow is employed to attach the IC 100 to the contact pad 112 on the carrier 114.
However, despite the widespread use of C4 technology, the current solder bump and BLM dimensions have resulted in cracking and metal layer separation at the chip level after attachment to a carrier. In addition, with the introduction of high yield stress lead free solder, low strength low-k dielectric materials, and new BLM structures additional failure modes are occurring, especially in organic flip chips that are governed by peeling (out-of-plane tension) rather than shear forces. However, there is presently no inexpensive and quick way to identify weakness of a particular combination of solder alloy, chip dielectric, and BLM structure without going through an expensive and time consuming chip assembly process. Present testing methods include mechanically holding the C4 solder ball and pulling it. However, this method suffers from major disadvantages, including the possibility of squeezing the C4 ball, and may not work for all solder alloys. The method also does not work if the solder volume is below certain critical volume, which varies with the diameter of the BLM pad. Another method, which involves attaching the chip to a chip carrier and pulling the entire chip suffers from a different disadvantage, wherein the effect of individual laminate design cannot be separated from the test data. Therefore, there is a need for an inexpensive, reliable, and repeatable test for peel strength of C4 chip connections.